1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems, and more particularly to a system and method for evaluating a netlist of an integrated circuit to detect storage nodes that are susceptible to begin left to undesirably float.
2. Discussion of the Related Art
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor xe2x80x9cchipxe2x80x9d in which the components are interconnected to perform a given function such as a microprocessor, programmable logic device (PLD), electrically erasable programmable memory (EEPROM), random access memory (RAM), operational amplifier, or voltage regulator. A circuit designer typically designs the integrated circuit by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and ensure performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated, electronic devices include electrical analog, digital, mixed hardware, optical, electromechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today""s sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A xe2x80x9cnetlistxe2x80x9d is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a xe2x80x9cnetlistxe2x80x9d is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often a netlist will contain a number of circuit xe2x80x9cmodulesxe2x80x9d which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by xe2x80x9cblack boxes.xe2x80x9d As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These xe2x80x9cblack boxxe2x80x9d representations, hereinafter called xe2x80x9cmodulesxe2x80x9d, will mask the complexities therein, typically showing only input/output ports.
An integrated circuit design can be represented at different levels of bstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are full-adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc. (purchased by Synopsys). PathMill is a transistor-based analysis tool used to find critical paths and verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. For example, there is often a need to identify certain logic gates or particular combinations of logic gates. More specifically, there is often a need to identify combinations of gates that are configured in such a manner that may lead to operational uncertainty or performance problems.
By way of particular example, it is sometimes undesirable for certain nodes in a circuit to be left floating. For example, nodes that act as input nodes to other devices, if left floating, can create noise in the circuit, since the circuitry receiving the input node may react as though the floating input is toggling between high and low states, or otherwise varying the input.
Accordingly, it is generally desirable to identify such potentially deleterious nodes during a circuit design phase, in order to obtain a higher quality circuit design.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a system and method for identifying nodes in a circuit design that are susceptible to floating. In accordance with one aspect of the invention, a method identifies nodes susceptible to floating by first detecting a node that is an output of a pass gate. The method then evaluates the circuit structure surrounding the node to ensure that the surrounding circuit structure is not one of several permissible structures. In this regard, the method ensures that the node is not an output node of a static gate. It also determines that the node is not an output of a multiplexer. If further verifies that the node is not an output of a pass gate that is always on. In addition, the method determines that the node drives a FET gate.
In accordance with the preferred embodiment, the method includes the step of ensuring that the node does not include a NFET channel-connected to Ground having a gate that is the static inverse of the gate of the pass gate, and ensuring that the node does not include a PFET channel connected to VDD having a gate that is the same sense (i.e., not the static inverse) as the gate of the pass gate. It will be appreciated that this determination may be made xe2x80x9con the fly,xe2x80x9d or alternatively certain static timing analyzing programs (such as PathMill) may identify static inverse nodes, whereby the preferred embodiment of the present invention may simply utilize this information in carrying out the method.
In accordance with another aspect of the present invention a method may be provided for determining whether a node is susceptible to floating. In operation the method ensures that the node is an output of a pass gate and verifies that only one pass gate drives the node. In addition the method ensures that the node is not an output node of a static gate and determines that the node drives a FET gate. In accordance with a preferred embodiment, the method also ensures that the node does not include a channel-connected FET having a gate that is the static inverse of the gate of the pass gate.
In accordance with yet another aspect of the invention, a computer readable storage medium containing program code for evaluating a netlist to detect a node that is susceptible to floating comprising. In this regard, the computer readable medium includes a first code segment configured to detect a node that is an output of a pass gate. It further includes a second code segment configured to ensure that the node is not an output node of a static gate. In addition, the computer readable medium includes a third code segment configured to determine that the node is not an output of a multiplexer. It further includes a fourth code segment configured to verify that the node is not an output of a pass gate that is always on. Finally, the computer readable medium includes a fifth code segment configured to determine that the node drives a FET gate. Preferably, the computer readable storage medium also includes a sixth code segment configured to ensure that the node does not include a channel-connected FET having a gate that is the static inverse of the gate of the pass gate.